Reconfigurable Supercomputing Session: S03: Reconfigurable Supercomputing Event Type: Tutorial Time: 8:30am - 5:00pm Speaker(s): Tarek El-Ghazawi, Duncan Buell, Kris Gaj, David B. Pointer Location: 606 Abstract: Advances in high-performance computing and in reconfigurable computing have resulted in reconfigurable supercomputing. Systems of microprocessors and field programmable gate arrays (FPGAs) can support both fine-grain and coarse-grain parallelism, and can tune their architecture to applications. This has led to three developments: networks of reconfigurable computers (NORCs), where networked reconfigurable resources can be exploited in a grid computing fashion; reconfigurable clusters, and reconfigurable parallel architectures. Programming these systems can be challenging, since programming FPGAs can involve hardware design. However, there have been significant developments in compilers and programming tools. This tutorial will introduce the field of reconfigurable supercomputing and its advances in systems, programming, applications, and tools. Reconfigurable systems from SRC, Cray, SGI, and Star Bridge as well as COTS based efforts will be considered. Application developments and performance studies will be presented. A comparative case study will be demonstrated from development to compilation and running across the aforementioned platforms. Introductory: 30% Intermediate: 40% Advanced: 30% Chair/Speaker Details: Tarek El-Ghazawi The George Washington University Duncan Buell U of South Carolina Kris Gaj George Mason University David B. Pointer U of Illinois at Urbana-Champaign